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preliminary product information this document contains information for a new product. cirrus logic reserves the right to modify this product without notice. 1 copyright ? cirrus logic, inc. 1999 (all rights reserved) p.o. box 17847, austin, texas 78760 (512) 445 7222 fax: (512) 445 7581 http://www.cirrus.com cs4227 six channel, 20-bit codec features l stereo 20-bit a/d converters l six 20-bit d/a converters l 108 db dac signal-to-noise ratio (eiaj) l mono 20-bit a/d converter l programmable input gain & output attenuation l on-chip anti-aliasing and output smoothing filters l de-emphasis for 32 khz, 44.1 khz, 48 khz description the cs4227 is a single-chip codec providing stereo an- alog-to-digital and six digital-to-analog converters using delta-sigma conversion techniques. this +5 v device also contains volume controls that are independently se- lectable for each of the six d/a channels. applications include dolby ? pro-logic?, thx ? , and dolby digital ac- 3? home theater systems, dsp based car audio sys- tems, and other multi-channel applications. ordering information cs4227-kq -10 to +70 c 44-pin tqfp CS4227-BQ -40 to +85 c 44-pin tqfp cdb4227 evaluation board i scl/cclk dem sda/cdout vd+ aout1 lrck sclk sdin1 sdout1 serial audio data interface control port digital filters dac#1 right adc left adc volume control analog low pass and output stage va+ aout2 ain1l ain1r sdin2 sdout2 ovl dac#4 dac#2 dac#3 dem mux clock osc/ divider clkout xti xto volume control volume control volume control lrckaux sclkaux dgnd1 dgnd2 auxiliary input input gain aout3 aout4 voltage reference ain2l ain2r ain3l ain3r input mux agnd2 sdin3 pdn ad1/cdin ad0/cs spi /i 2 c cmout dac#6 dac#5 volume control volume control aout5 aout6 mono adc ainaux agnd1 dataux hold digital filters sep 99 ds281pp2
cs4227 2 ds281pp2 table of contents 1. characteristics and specifications ........................................................................ 4 analog characteristics ................................................................................................ 4 switching characteristics .......................................................................................... 6 switching characteristics - control port........................................................... 8 absolute maximum ratings ......................................................................................... 10 recommended operating conditions ..................................................................... 10 digital characteristics ............................................................................................... 10 2. functional description ............................................................................................... 12 2.1 overview .................................................................................................................. ........ 12 2.2 analog inputs ............................................................................................................. ...... 12 2.2.1 line level inputs ................................................................................................. 12 2.2.2 adjustable input gain .......................................................................................... 13 2.2.3 high pass filter ................................................................................................... 13 2.3 analog outputs ............................................................................................................ .... 13 2.3.1 line level outputs .............................................................................................. 13 2.3.2 output level attenuator ...................................................................................... 14 2.4 clock generation .......................................................................................................... ... 14 2.4.1 clock source ....................................................................................................... 14 2.4.2 master clock output ........................................................................................... 14 2.4.3 synchronization ................................................................................................... 14 2.5 digital interfaces ........................................................................................................ ...... 15 2.5.1 audio dsp serial interface signals ..................................................................... 15 2.5.2 audio dsp serial interface formats ................................................................... 15 2.5.3 auxiliary audio port signals ................................................................................ 15 2.5.4 auxiliary audio port formats ............................................................................... 15 2.6 control port signals ...................................................................................................... ... 17 2.6.1 spi mode ............................................................................................................ 17 2.6.2 i 2 c ? mode ........................................................................................................... 18 2.6.3 control port bit definitions .................................................................................. 18 2.7 power-up/reset/power down mode ................................................................................ 18 2.8 dac calibration ........................................................................................................... .... 19 2.9 de-emphasis ............................................................................................................... .... 19 2.10 hold function ............................................................................................................ ..... 19 contacting cirrus logic support for a complete listing of direct sales, distributor, and sales representative contacts, visit the cirrus logic web site at: http://www.cirrus.com/corporate/contacts/ dolby is a registered trademark of dolby labratories licensing corporation. pro logic, and ac-3 are trademarks of dolby labratories licensing corporation. thx is a registered trademark of lucasarts entertainment company. preliminary product information describes products which are in production, but for which full characterization data is not yet available. advance product infor- mation describes products which are in development and subject to development changes. cirrus logic, inc. has made best effort s to ensure that the information contained in this document is accurate and reliable. however, the information is subject to change without notice and is provi d ed as is without warranty of any kind (express or implied). no responsibility is assumed by cirrus logic, inc. for the use of this information, nor for inf ringements of patents or other rights of third parties. this document is the property of cirrus logic, inc. and implies no license under patents, copyrights, tradem arks, or trade secrets. no part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electron ic, mechanical, photographic, or otherwise) without the prior written consent of cirrus logic, inc. items from any cirrus logic website or disk may be printed for use by the user. however, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form o r by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of cirrus logic, inc.furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of cirrus logic, inc. the names of products of cirrus logic, inc. or ot her vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. a list of cirrus logic, inc. trade- marks and service marks can be found at http://www.cirrus.com.
cs4227 ds281pp2 3 2.11 power supply, layout, and grounding .......................................................................... 19 2.12 adc and dac filter response plots ............................................................................ 20 3. pin descriptions .......................................................................................................... .... 29 4. parameter definitions .................................................................................................. 33 5. package dimensions ...................................................................................................... 34 list of figures figure 1. audio ports master mode timing..................................................................................... 7 figure 2. audio ports slave mode and data i/o timing ................................................................. 7 figure 3. control port spi mode ................................................................................................ ..... 8 figure 4. control port i 2 c mode...................................................................................................... 9 figure 5. recommended connection diagram............................................................................. 11 figure 6. optional line intput buffer .......................................................................................... ... 12 figure 7. butterworth filters.................................................................................................. ........ 13 figure 8. audio dsp and auxiliary port data input formats ........................................................ 16 figure 9. audio dsp port data output formats ........................................................................... 16 figure 10. one data line modes ................................................................................................. .16 figure 11. control port timing, spi mode .................................................................................... 17 figure 12. control port timing, i 2 c ? mode................................................................................... 18 figure 13. de-emphasis curve. .................................................................................................. .. 19 figure 14. suggested layout guideline........................................................................................ 20 figure 15. 20-bit adc filter response ......................................................................................... 2 1 figure 16. 20-bit adc passband ripple ....................................................................................... 21 figure 17. 20-bit adc transition band ......................................................................................... 2 1 figure 18. dac frequency response .......................................................................................... 21 figure 19. dac passband ripple ................................................................................................. 21 figure 20. dac transition band ................................................................................................. .. 21 list of tables table 1. single-ended vs differential input pin assignments .............................................................. 12 table 2. high pass filter characteristics ...................................................................................... ...... 13 table 3. dsp serial input ports................................................................................................ ........... 15
cs4227 4 ds281pp2 1. characteristics and specifications analog characteristics (t a = 25 c; va+, vd+ = +5 v; full scale input sine wave, 997 khz; fs = 44.1 khz; measurement bandwidth is 20 hz to 20 khz; local components as shown in figure 5; spi mode, format 3, unless otherwise specified.) notes: 1. referenced to typical full-scale differential input voltage (2vrms). 2. input resistance is for the input selected. non-selected inputs have a very high (>1m w ) input resistance. the input resistance will vary with gain value selected, but will always be greater than the min. value specified. 3. filter characteristics scale with output sample rate. 4. the analog modulator samples the input at 5.6448 mhz for an output sample rate of 44.1 khz. there is no rejection of input signals which are multiples of the sampling frequency (n x 5.6448 mhz 20.0 khz where n = 0,1,2,3...). 5. group delay for fs = 44.1 khz, t gd = 15/44.1 khz = 340 s parameter symbol cs4227-kq CS4227-BQ units min typ max min typ max analog input characteristics - minimum gain setting (0 db) differential input; unless otherwise specified. adc resolution stereo audio channels mono channel 16 16 - - 20 20 16 16 - - 20 20 bits bits total harmonic distortion thd 0.003 - 0.003 - % dynamic range (a weighted, stereo) (unweighted, stereo) (a weighted, mono) 92 - 89 95 92 - - - - 90 - 87 93 90 - - - - db db db total harmonic -1 db, stereo (note 1) distortion + noise -1 db, mono (note 1) thd+n - - -88 - -82 -72 - - -86 - -80 -70 db db interchannel isolation - 90 - - 90 - db interchannel gain mismatch - 0.1 - - 0.1 - db programmable input gain span 8 9 10 8 9 10 db gain step size 2.7 3 3.3 2.7 3 3.3 db offset error (with high pass filter) - - 0 - - 0 lsb full scale input voltage (single ended): 0.90 1.0 1.10 0.90 1.0 1.10 vrms gain drift - 100 - - 100 - ppm/c input resistance (note 2) 10 - - 10 - - k w input capacitance - - 15 - - 15 pf cmout output voltage - 2.3 - - 2.3 - v a/d decimation filter characteristics passband (note 3) 0.02 - 20.0 0.02 - 20.0 khz passband ripple - - 0.01 - - 0.01 db stopband (note 3) 27.56 - 5617.2 27.56 - 5617.2 khz stopband attenuation (note 4) 80 - - 80 - - db group delay (fs = output sample rate) (note 5) t gd - 15/fs - - 15/fs - s group delay variation vs. frequency d t gd --0--0 m s
cs4227 ds281pp2 5 analog characteristics (continued) notes: 6. the passband and stopband edges scale with frequency. for input word rates, fs, other than 44.1 khz, the 0.05 db passband edge is 0.4535xfs and the stopband edge is 0.5465xfs. 7. digital filter characteristics. 8. measurement bandwidth is 10 hz to 3fs. specifications are subject to change without notice parameter symbol cs4227-kq CS4227-BQ units min typ max min typ max high pass filter characteristics frequency response: -3 db (note 3) -0.13 db - - 3.4 20 - - - - 3.4 20 - - hz hz phase deviation @ 20 hz (note 3) - 10 - - 10 - deg. passband ripple - - 0 - - 0 db analog output characteristics - minimum attenuation, 10 k, 100 pf load; unless otherwise specified. dac resolution 16 - 20 16 - 20 bits signal-to-noise/idle (dac muted, a weighted) channel noise 101 108 - 99 106 - db dynamic range (dac not muted, a weighted) (dac not muted, unweighted) 93 - 98 95 - - 91 - 96 93 - - db db total harmonic distortion thd - 0.003 - - 0.003 - % total harmonic distortion + noise (stereo) thd+n - -88 -83 - -86 -81 db interchannel isolation - 90 - - 90 - db interchannel gain mismatch - 0.1 - - 0.1 - db attenuation step size (all outputs) 0.7 1 1.3 0.7 1 1.3 db programmable output attenuation span -84 -86 - -84 -86 - db offset voltage (relative to cmout) - 15 - - 15 - mv full scale output voltage 0.92 1.0 1.08 0.92 1.0 1.08 vrms gain drift - 100 - - 100 - ppm/c out-of-band energy (fs/2 to 2fs) - -60 - - -60 - dbfs analog output load resistance: capacitance: 10 - - - - 100 10 - - - - 100 k w pf combined digital and analog filter characteristics frequency response 10 hz to 20 khz - 0.1 - - 0.1 - db deviation from linear phase - 0.5 - - 0.5 - deg. passband: to 0.01 db corner (notes 6, 7) 0 - 20.0 0 - 20.0 khz passband ripple (note 7) - - 0.01 - - 0.01 db stopband (notes 6 ,7) 24.1 - - 24.1 - - khz stopband attenuation (note 8) 70 - - 70 - - db group delay (fs = input word rate) (note 5) tgd - 16/fs - - 16/fs - s analog loopback performance signal-to-noise ratio (ccir-2k weighted, -20 db input) ccir-2k -71- -71- db power supply power supply current operating power down - - 90 1 113 3 - - 90 1 115 3 ma ma power supply rejection (1 khz, 10 mv rms ) - 45 - - 45 - db
cs4227 6 ds281pp2 switching characteristics (t a = 25 c; va+, vd+ = +5 v 5%; outputs loaded with 30 pf.) notes: 9. clkout jitter is for 256x fs selected as output frequency measured from falling edge to falling edge. jitter is greater for 384x fs and 512x fs as selected output frequency. 10. for clkout frequency equal to 1x fs, 384x fs, and 512x fs. see master clock output section. 11. after powering up the cs4227, pdn should be held low for 1 ms to allow the power supply to settle. 12. 13. 14. parameter symbol min typ max unit audio adcs and dacs sample rate fs 4 - 50 khz xti frequency xti = 256, 384, or 512 fs 1.024 - 26 mhz xti pulse width high xti = 512 fs xti = 384 fs xti = 256 fs 10 21 31 - - - - - - ns xti pulse width low xti = 512 fs xti = 384 fs xti = 256 fs 10 21 31 - - - - - - ns xti jitter tolerance - 500 - ps clkout jitter (note 9) - 200 - psrms clkout duty cycle (high timer/cycle time) (note 10) 40 50 60 % pdn low time (note 11) 500 - - ns sclk falling edge to sdout output valid dsck = 0 t dpd - - note 12 ns lrck edge to msb valid t lrpd - - 40 ns sdin setup time before sclk rising edge dsck = 0 t ds - - 25 ns sdin hold time after sclk rising edge dsck = 0 t dh - - 25 ns master mode sclk falling to lrck edge dsck = 0 t mslr -10-ns sclk period (note 14) - - - - - sclk duty cycle - 50 - % slave mode sclk period t sckw note 13 - - ns sclk high time t sckh 40 - - ns sclk low time t sckl 40 - - ns sclk rising to lrck edge dsck = 0 t lrckd 20 - - ns lrck edge to sclk rising dsck = 0 t lrcks 40 - - ns 1 384 () fs --------------------- 2 0 + 1 128 () fs --------------------- 1 256 () fs -------------------
cs4227 ds281pp2 7 t mslr sclk* sclkaux* (output) lrck lrckaux (output) sdout1 sdout2 sckh sckl sckw t t t msb msb-1 *sclk, sclkaux shown for dsck = 0 and asck = 0. sclk & sclkaux inverted for dsck = 1 and asck = 1, respectively. t dpd sdout1 sdout2 lrckaux (input) lrck sclk* sclkaux* (input) sdin1 sdin2 dataux dh t ds t lrpd t lrcks t lrckd t sdin3 figure 1. audio ports master mode timing figure 2. audio ports slave mode and data i/o timing
cs4227 8 ds281pp2 switching characteristics - control port (t a = 25 c; va+, vd+ = +5 v 5%; inputs: logic 0 = dgnd, logic 1 = vd+; c l = 30 pf) notes: 15. data must be held for sufficient time to bridge the transition time of cclk. 16. for f sck < 1 mhz. parameter symbol min max unit spi mode (spi /i2c = 0) cclk clock frequency f sck -6mhz cs high time between transmissions t csh 1.0 - s cs falling to cclk edge t css 20 - ns cclk low time t scl 66 - ns cclk high time t sch 66 - ns cdin to ccl rising setup time t dsu 40 - ns cclk rising to data hold time (note 15) t dh 15 - ns cclk falling to cdout stable t pd -45ns rise time of cdout t r1 -25ns fall time of cdout t f1 -25ns rise time of cclk and cdin (note 16) t r2 - 100 ns fall time of cclk and cdin (note 16) t f2 - 100 ns t r2 t f2 t dsu t dh t sch t scl cs cclk cdin t css t pd cdout t csh figure 3. control port spi mode
cs4227 ds281pp2 9 switching characteristics - control port (t a = 25 c; va+, vd+ = +5 v 5%; inputs: logic 0 = dgnd, logic 1 = vd+; c l = 30 pf) notes: 17. i 2 c ? is a registered trademark of philips semiconductors. 18. data must be held for sufficient time to bridge the 300 ns transition time of scl. parameter symbol min max unit i 2 c ? mode (spi /i2c = 1) (note 17) scl clock frequency f scl -100khz bus free time between transmissions t buf 4.7 - s start condition hold time (prior to first clock pulse) t hdst 4.0 - s clock low time t low 4.7 - s clock high time t high 4.0 - s setup time for repeated start condition t sust 4.7 - s sda hold time for scl falling (note 18) t hdd 0-s sda setup time to scl rising t sud 250 - ns rise time of both sda and scl lines t r -1s fall time of both sda and scl lines t f - 300 ns setup time for stop condition t susp 4.7 - s t buf t hdst t hdst t low t r t f t hdd t high t sud t sust t susp stop start start stop repeated sda scl figure 4. control port i 2 c mode
cs4227 10 ds281pp2 absolute maximum ratings (agnd, dgnd = 0 v, all voltage with respect to 0 v.) notes: 19. any pin except supplies. transient currents of up to 100 ma on the analog input pins will not cause scr latch-up. 20. the maximum over or under voltage is limited by the input current. warning: warning:operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (agnd, dgnd = 0 v, all voltage with respect to 0 v.) digital characteristics (t a = 25 c; va+, vd+ = +5 v 5%) parameter symbol min max unit power supplies digital analog vd+ va+ -0.3 -0.3 6.0 6.0 v input current (note 19) - 10 ma analog input voltage (note 20) -0.7 (va+) + 0.7 v digital input voltage (note 20) -0.7 (vd+) + 0.7 v ambient temperature (power applied) -55 +125 c storage temperature -65 +150 c parameter symbol min typ max unit power supplies digital |va+ - vd+| < 0.4 v analog vd+ va+ 4.75 4.75 5.0 5.0 5.25 5.25 v operating ambient temperature t a -10 25 70 c parameter symbol min max unit high-level input voltage (except xti) v ih 2.8 (vd+) + 0.3 v low-level input voltage (except xti) v il -0.3 0.8 v high-level output voltage (except xto) v oh (vd+) - 1.0 - v low-level output voltage (except xto) v ol -0.4v input leakage current (digital inputs) - 10 a output leakage current (high-impedance digital outputs) - 10 a
cs4227 ds281pp2 11 +5v supply ferrite bead + 1 m f 0.1 m f 19 2.0 w + 1 m f 0.1 m f 40 va+ vd+ agnd1, 2 dgnd1, 2 nc xto xti 17 c1** c2** 29 28 external clock input 39 41 20 18 21 * optional if analog inputs biased to within 1% of cmout aout1 22 aout2 23 aout3 24 aout4 25 aout5 26 aout6 3 4 6 5 microcontroller scl/cclk sda/cdout ad0/cs ad1/cdin 34 33 32 36 audio dsp sdin1 sdin2 sdin3 sdout1 35 37 38 31 30 sdout2 lrck sclk clkout ovl r s r s 16 15 10 m f 1 m f cmout 14 10 m f to optional input and output buffers ain1l 13 10 m f ain1r 11 10 m f ain2l 12 10 m f ain2r 10 10 m f ain3l 9 10 m f ain3r 1 44 43 dataux lrckaux sclkaux r s r s ainaux digital audio source 8 pdn 7 spi/i2c mode setting all unused digital inputs should be tied to 0v. unused analog inputs should be left unconnected. cs4227 2 hold 27 dem analog filter analog filter analog filter analog filter analog filter analog filter * * * * * * * from optional input buffer + r = 50 w s figure 5. recommended connection diagram (also see recommended layout diagrams, figure 14)
cs4227 12 ds281pp2 2. functional description 2.1 overview the cs4227 has 2 channels of 20-bit analog-to- digital conversion and 6 channels of 20-bit digital- to-analog conversion. a mono 20-bit adc is also provided. all adcs and dacs are delta-sigma converters. the stereo adc inputs have adjustable input gain, while the dac outputs have adjustable output attenuation. digital audio data received by the dacs and trans- mitted from the adcs is communicated over sepa- rate serial ports, allowing concurrent writing to and reading from the device. the cs4227 functions are controlled via a serial microcontroller interface. figure 1 shows the recommended connection dia- gram for the cs4227. 2.2 analog inputs 2.2.1 line level inputs ain1r, ain1l, ain2r, ain2l, ain3r, ain3l and ainaux are the line level input pins (see fig- ure 5). these pins are internally biased to the cmout voltage (nominally 2.3 v). a 10 f dc blocking capacitor allows signals centered around 0 v to be input. figure 6 shows an optional dual op amp buffer which combines level shifting with a gain of 0.5 to attenuate the standard line level of 2v rms to 1 v rms . the cmout reference level is used to bias the op-amps to approximately one half the supply voltage. with this input circuit, the 10 f dc blocking caps in figure 5 may be omit- ted. any remaining dc offset will be removed by the internal high-pass filters. selection of the stereo input pair for the 20-bit adc's is accomplished by setting the ais1/0 bits, which are accessible in the adc control byte. on- chip anti-aliasing filters follow the input mux, pro- viding anti-aliasing for all input channels. the analog inputs may also be configured as differ- ential inputs. this is enabled by setting bits ais1/0 = 3. in the differential configuration, the left channel inputs reside on pins 10 and 11, and the right channel inputs reside on pins 12 and 13 as de- scribed in the table below. in differential mode, the full scale input level is 2 v rms . table 1. single-ended vs differential input pin assignments the analog signal is input to the mono adc via the ainaux pin. independent muting of both the stereo adc's and the mono adc is possible through the adc con- trol byte (#11) with the mutr, mutl and mutm bits. single-ended pin # differential inputs ain3l pin 10 ainl+ ain3r pin 9 unused ain2l pin 11 ainl- ain2r pin 12 ainr- ain1l pin 14 unused ain1r pin 13 ainr+ + - 100 pf 10 k 20 k + - 10 k 100 pf 5 k 20 k line in right line in left cmout ainxr ainxl 0.47 m f 3.3 m f 3.3 m f example op-amps are mc34074 or mc33078 figure 6. optional line intput buffer
cs4227 ds281pp2 13 2.2.2 adjustable input gain the signals from the line inputs are routed to a pro- grammable gain circuit which provides up to 9 db of gain in 3 db steps, adjustable through the input control byte. right and left channel gain settings are controlled independently with the gnr1/0 and gnl1/0 bits. to minimize audible artifacts, level changes should be done with the channel muted, as the changes occur immediately on register updates. the adc status report byte provides feedback of input level for each adc channel. this register continously monitors the adc output and records the peak output level since the last register read. reading this register causes it to reset to 0, where- upon peak monitoring begins again. 2.2.3 high pass filter the operational amplifiers in the input circuitry driving the cs4227 may generate a small dc offset into the a/d converter. the cs4227 includes a high pass filter after the decimator to remove any dc offset which could result in recording a dc lev- el, possibly yielding "clicks" when switching be- tween devices in a multichannel system. the characteristics of this first-order high pass fil- ter are outlined below for an output sample rate of 44.1 khz. this filter response scales linearly with sample rate. table 2. high pass filter characteristics 2.3 analog outputs 2.3.1 line level outputs the cs4227 contains an on-chip buffer amplifier producing single-ended outputs capable of driving 10 k w loads. each output (aout 1-6) will produce a nominal 2.83 v pp (1 v rms ) output with a 2.3 volt quiescent voltage for a full scale digital input. the recommended off-chip analog filter is a 2nd order butterworth with a -3 db corner at fs (see figure 7). this filter provides out-of-band noise at- tenuation along with a gain of 2, providing a 2 v rms output signal. a 3rd order butterworth filter with a -3 db corner at 0.75 fs can be used if greater out of band noise filtering is desired. the cs4227 dac interpolation filter is a linear phase design which has been pre-compensated for an external 2nd or- der butterworth filter to provide a flat frequency re- sponse and linear phase response over the passband. if this filter is not used, small frequency response magnitude and phase errors will occur. frequency response -3db @ 3.4 hz -0.13 db @ 20 hz phase deviation 10 degrees @ 20 hz passband ripple none _ 22 k w 150pf 3.9 k w 11 k w 1000pf + c mout 5 k w 0.47 m f example op-amps are mc33078 _ 5.85 k w 560 pf 1.21 k w 1.1 k w 5600 pf + c mout 5 k w 0.47 m f a out 4.75 k w 5600 pf 2-pole butterworth filter 3-pole butterworth filter figure 7. butterworth filters
cs4227 14 ds281pp2 2.3.2 output level attenuator the dac outputs are each routed through an atten- uator which is adjustable in 1 db steps. output at- tenuation is available through the output attenuator data bytes. level changes are imple- mented such that the noise is attenuated by the same amount as the signal (equivalent to using an analog attenuator after the signal source) until the residual output noise is equal to the noise floor in the mute state. level changes only take effect on zero crossings to minimize audible artifacts. if there is no zero crossing, then the requested level change will occur after a time-out period between 512 and 1024 frames (11.6 ms to 23.2 ms at 44.1 khz frame rate). there is a separate zero crossing detector for each channel. each acc bit in the dac status report byte provides informa- tion on when a volume control change has taken ef- fect. this bit goes high when a new setting is loaded and returns low when it has taken effect. volume control changes can be instantaneous by setting the zero crossing disable (zcd) bit in the dac control byte (#3) to 1. each output can be independently muted via mute control bits, mut6-1, in the dac control byte (#3). the mute also takes effect on a zero-crossing or after a timeout. in addition, the cs4227 has an optional mute on consecutive zeros feature, where all dac outputs will mute if they receive between 512 and 1024 consecutive zeros (or -1 code) on all six channels. a single non-zero value will unmute the dac outputs. this feature can be disabled with the mutc bit in the dac control byte (#3). 2.4 clock generation the master clock to operate the cs4227 may be generated by using the on-chip inverter and an ex- ternal crystal or by using an external clock source. if the active clock source stops for 10 s, the cs4227 will enter a power down state. in all modes it is required to have sclk and lrck synchro- nous to the selected master clock. 2.4.1 clock source the cs4227 requires a high frequency master clock to run the internal logic. the clock enable bit (ce) must be set to 0 after power-up of the device (see power-up/reset/power down mode section). a high frequency crystal can be connected to xti and xto, or a high frequency clock can be applied to xti. this high frequency clock can be 256 fs, 384 fs or 512 fs; this is set by the ci0/1 bits in the clock mode byte (#1). when using the on-chip crystal oscillator, external loading capacitors are required (see figure 5). high frequency crystals (>8 mhz) should be parallel resonant, fundamental mode and designed for 20 pf loading (equivalent to 40 pf to ground on each leg). 2.4.2 master clock output clkout is a master clock output provided to al- low synchronization of external components. available clkout frequencies of 1 fs, 256 fs, 384 fs, and 512 fs, are selectable by the co0/1 bits of the clock mode byte. generation of clkout for 384 fs and 512 fs is accomplished with an on chip clock multiplier and may contain clock jitter. the source of the 256 fs clkout is a divided down clock from the xti/xto input. if 384 fs is chosen as the input clock at xti and 256 fs is chosen as the output, clkout will have approximately a 33% duty cy- cle. in all other cases clkout will typically have a 50% duty cycle. 2.4.3 synchronization the dsp port and auxiliary port must operate syn- chronously to the cs4227 clock source. the serial port will force a reset of the data paths in an attempt to resynchronize if non-synchronous data is input to the cs4227. it is advisable to mute the dacs when changing from one clock source to another to avoid the output of undesirable audio signals as the cs4227 resynchronizes.
cs4227 ds281pp2 15 2.5 digital interfaces there are 2 digital audio interface ports: the audio dsp port and the auxiliary digital audio port. the serial data is represented in 2's complement format with the msb-first in all formats. 2.5.1 audio dsp serial interface signals the serial interface clock, sclk, is used for trans- mitting and receiving audio data. the active edge of sclk is chosen by setting the dsck bit in the dsp port mode byte (#14). sclk can be generat- ed by the cs4227 (master mode) or it can be input from an external sclk source (slave mode). mode selection is set with the dms1/0 bits in the dsp port mode byte (#14). the number of sclk cy- cles in one system sample period is programmable to be 32, 48, 64, or 128 by setting the dck1/0 bits in the dsp port mode byte (#14). when sclk is an input, 64 sclk's per system sample period is not recommended, due to potential interference ef- fects; if possible 128 sclk's per sample period should be used instead. for master mode, bursting of a 128 fs clock is preferrable over evenly distrib- uted clocks. the left/right clock (lrck) is used to indicate left and right data and the start of a new sample pe- riod. it may be output from the cs4227, or it may be generated from an external controller. the fre- quency of lrck must be equal to the system sam- ple rate, fs. sdin1, sdin2, and sdin3 are the data input pins, each of which drives a pair of dacs. sdout1 and sdout2 can carry the output data from the two 20-bit adc's, the mono adc and the auxiliary dig- ital audio port. selection depends on the is1/0 bits in the adc control byte (#11). the audio dsp port may also be configured so that all 6 dac's data is input on sdin1, and all 3 adc's data is output on sdout1. table 3 outlines the serial interface ports. table 3. dsp serial input ports 2.5.2 audio dsp serial interface formats the audio dsp port supports 7 alternate formats, shown in figures 8, 9, and 10. these formats are chosen through the dsp port mode byte (#14) with the ddf2/1/0 bits. formats 5 and 6 are single line data modes where all dac channels are combined onto a single input and all adc channels are combined onto a single output. format 6 is available in master mode only. see figure 10. 2.5.3 auxiliary audio port signals the auxiliary port provides an alternate way to in- put digital audio signals into the cs4227. this port consists of clock, data and left/right clock pins named, sclkaux, dataux and lrckaux. the auxiliary audio port input is output on sdout1 when is is set to 1 or 2 in the adc con- trol byte. additionally, setting is to 2 routes the stereo adc outputs to sdout2. there is approx- imately a two frame delay from dataux to sdout1. when the auxiliary port is used, the fre- quency of lrckaux must be equal to the system sample rate, fs, but no particular phase relationship is required. de-emphasis can be performed on input data to the auxiliary audio port; this is controlled by the aux- iliary port control byte (#16). 2.5.4 auxiliary audio port formats input data on dataux is clocked into the part by sclkaux using the format selected in the auxil- iary port mode byte. the auxiliary audio port sup- dac inputs sdin1 left channel right channel single line dac #1 dac #2 all 6 dac channels sdin2 left channel right channel dac #3 dac #4 sdin3 left channel right channel dac #5 dac #6
cs4227 16 ds281pp2 lrck format 0, 1, 2: sclk sdin format 0: m = 20 format 1: m = 18 format 2: m = 16 lsb lsb msb lsb msb left right m sclks m sclks lrck format 3: sclk sdin msb lsb left right msb lsb msb lrck format 4: sclk sdin msb lsb left right msb lsb note: sclk shown for dsck = 0. sclk inverted for dsck = 1. figure 8. audio dsp and auxiliary port data input formats lrck format 0, 1, 2: sclk sdout format 0: m = 20 format 1: m = 18 format 2: m = 16 lsb lsb msb lsb msb left right m sclks m sclks lrck format 3: sclk sdout msb lsb left right msb lsb msb lrck format 4: sclk sdout msb lsb left right msb lsb note: sclk shown for dsck = 0. sclk inverted for dsck = 1. figure 9. audio dsp port data output formats lrck format 5: sclk sdin1 lsb msb 20 clks 64 sclks 64 sclks lsb msb lsb msb lsb msb lsb msb lsb msb msb dac #1 dac #3 dac #5 dac #2 dac #4 dac #6 20 clks 20 clks 20 clks 20 clks 20 clks 20 clks sdout1 sdout2 sdout1 sdout2 20 clks 20 clks 20 clks sdout1 lrck format 6: sclk sdin1 lsb msb 32 clks 128 sclks 128 sclks dac #1 dac #3 dac #5 32 clks 32 clks 32 clks sdout1 sdout2 32 clks sdout1 lsb msb lsb msb lsb msb 32 clks dac #2 dac #4 dac #6 32 clks 32 clks 32 clks sdout1 sdout2 32 clks lsb msb lsb msb (master mode only) figure 10. one data line modes
cs4227 ds281pp2 17 ports the same 5 formats as the audio dsp port in multi-data line mode. lrckaux is used to indi- cate left and right data samples, and the start of a new sample period. sclkaux and lrckaux may be output from the cs4227, or they may be generated from an external source, as set by the ams1/0 control bits in the auxiliary port mode byte (#15). 2.6 control port signals the control port is used to load all the internal set- tings. the operation of the control port may be completely asynchronous with the audio sample rate. however, to avoid potential interference prob- lems, the control port pins should remain static if no operation is required. the control port has 2 modes: spi and i 2 c ? , with the cs4227 as a slave device. the spi mode is se- lected by setting the spi /i2c pin low, and i 2 c ? is selected by setting the spi /i2c pin high. the state of this pin is continuously monitored. 2.6.1 spi mode in spi mode, cs is the cs4227 chip select signal, cclk is the control port bit clock, (input into the cs4227 from the microcontroller), cdin is the in- put data line from the microcontroller, cdout is the output data line to the microcontroller, and the chip address is 0010000. data is clocked in on the rising edge of cclk and out on the falling edge. figure 11 shows the operation of the control port in spi mode. to write to a register, bring cs low. the first 7 bits on cdin form the chip address, and they must be 0010000. the eighth bit is a read/write in- dicator (r/w ), which should be low to write. the next 8 bits form the memory address pointer (map), which is set to the address of the register that is to be updated. the next 8 bits are the data which will be placed into register designated by the map. during writes, the cdout output stays in the high impedance state. it may be externally pulled high or low with a 47 k w resistor. the cs4227 has a map auto increment capability, enabled by the incr bit in the map register. if incr is a zero, then the map will stay constant for successive reads or writes. if incr is set to a 1, then map will auto increment after each byte is read or written, allowing block reads or writes of successive registers. to read a register, the map has to be set to the cor- rect address by executing a partial write cycle which finishes (cs high) immediately after the map byte. the auto map increment bit (incr) may be set or not, as desired. to begin a read, bring cs low, send out the chip address and set the read/write bit (r/w ) high. the next falling edge of cclk will clock out the msb of the addressed register (cdout will leave the high impedance state). if the map auto increment bit is set to 1, the data for successive registers will appear consecu- tively. map msb lsb data byte 1 byte n r/w r/w high impedance map = memory address pointer address chip address chip cdin cclk cs cdout msb lsb msb lsb 0010000 0010000 figure 11. control port timing, spi mode
cs4227 18 ds281pp2 2.6.2 i 2 c ? mode in i 2 c ? mode, sda is a bidirectional data line. data is clocked into and out of the part by the clock, scl, with the clock to data relationship as shown in figure 12. there is no cs pin. pins ad0, ad1 form the partial chip address. the upper 5 bits of the 7 bit address field must be 00100. to commu- nicate with a cs4227, the lsbs of the chip address field, which is the first byte sent to the cs4227, should match the settings of the ad1, ad0 pins. the eighth bit of the address bit is the r/w bit (high for a read, low for a write). if the operation is a write, the next byte is the memory address pointer which selects the register to be read or written. if the operation is a read, the contents of the register pointed to by the memory address pointer will be output. setting the auto increment bit in map, al- lows successive reads or writes of consecutive reg- isters. each byte is separated by an acknowledge bit. use of the i 2 c bus ? compatible interface re- quires a license from philips. i 2 c bus ? is a regis- tered trademark of philips semiconductors. 2.6.3 control port bit definitions all registers can be written and read back, except the dac status report byte (#10) and adc status report byte (#13), which are read only. see the fol- lowing bit definition tables for bit assignment in- formation. 2.7 power-up/reset/power down mode upon power up, the user should hold pdn = 0 for approximately 1ms. in this state, the control port is reset to its default settings. at the end of the pdn , the device remains in a low power mode in which cmout will not supply current, but the control port is active. the desired settings should be loaded while keeping the rs bit set to 1. normal operation is achieved by setting the ce bit to zero in the clock mode byte (#1) and the rs bit to zero in the converter control byte (#2). once done, the part powers up and an offset calibration occurs. this process lasts approximately 50 ms. reset/power down is achieved by lowering the pdn pin causing the part to enter power down. once pdn goes high, the control port is functional and the desired settings should be loaded in while keeping the rs bit set to 1. the remainder of the chip remains in a low power reset state until the rs bit in the convertor control byte is set to 0. after clearing the rs bit, the ce bit (clock enable) in the clock mode byte (#1) should also be set to zero. the cs4227 will also enter a stand by mode if the master clock source stops for approximately 10 s or if the lrck is not synchronous to the master clock. the control port will retain its current set- tings. sda scl 00100 addr ad1-0 r/w start ack data 1-8 ack data 1-8 ack stop note 1: if operation is a write, this byte contains the memory address pointer, map. note 1 figure 12. control port timing, i 2 c ? mode
cs4227 ds281pp2 19 2.8 dac calibration output offset voltage is minimized by an internal calibration cycle. a calibration will automatically occur anytime the part comes out of reset, includ- ing the power-up reset, or when the master clock source to the part changes by changing the ce or ci bits in the clock mode byte. the cs4227 can be re-calibrated whenever de- sired. a control bit, cal, in the converter control byte, is provided to initiate a calibration. the se- quence is: 1) set cal to 1, the cs4227 sets calp to 1 and begins to calibrate. 2) calp will go to 0 when the calibration is com- pleted. additional calibrations can be implemented by set- ting cal to 0 and then to 1. 2.9 de-emphasis the cs4227 is capable of digital de-emphasis for 32, 44.1, or 48 khz sample rates. implementation of digital de-emphasis requires reconfiguration of the digital filter to maintain the filter response shown in figure 13 at multiple sample rates. the auxiliary port control byte selects the de-empha- sis control method. de-emphasis may be enabled under hardware control, using the dem pin (dem2/1/0=4,5,6), or by software control using the dem bit (dem2/1/0=0,1,2,3) 2.10 hold function if the digital audio source presents invalid data to the cs4227, the cs4227 may be configured to cause the last valid digital input level to be held constant (this sounds much better than a potentially random output level). holding the previous output sample occurs when the user asserts the hold pin (hold = 1) at any time during the stereo sample period. during a hold condition, auxport input data is ignored. dac outputs can be automatically muted after an extended hold period (>15 sam- ples) by setting the moh bit = 0 in the auxiliary port control byte. dacs will not be automatically muted when moh = 1. when the hold pin is de- asserted (hold = 0), the dac outputs will return to one of two different states controlled by the umv (unmute on valid data) bit in the auxiliary port control byte. when umv = 0, the dac out- puts will unmute when the hold is removed. when umv = 1, the dacs must be unmuted in the dac control byte after the hold is removed. this allows the user to unmute the dac after the invalid data has passed through the dsp. 2.11 power supply, layout, and grounding the cs4227, along with associated analog circuit- ry, should be positioned near the split between ground planes, and have its own, separate, ground plane (see figure 14). preferably, it should also have its own power plane. the +5 v supply must be connected to the cs4227 via a ferrite bead, posi- tioned closer than 1" to the device. a single con- nection between the cs4227 ground and the board ground should be positioned as shown in figure 14. the location of the 1 f cmout filtering capica- tor should be as close to the cs4227 as possible. see crystal's layout applications note, and the cdb4227 evaluation board data sheet for recom- mended layout of the decoupling components. gain db -10db 0db frequency t2 = 15 m s t1=50 m s f1 f2 figure 13. de-emphasis curve.
cs4227 20 ds281pp2 the cs4227 will mute the analog outputs and enter the power down mode if the supply drops below approximately 4 volts. 2.12 adc and dac filter response plots figures 15 through 20 show the overall frequency response, passband ripple and transition band for the cs4227 adc's and dac's. digital ground plane note that the cs4227 is oriented with its digital pins towards the digital end of the board. cpu & digital logic codec digital signals analog ground plane 1/8" > cs4227 +5v ferrite bead ground connection codec analog signals & components figure 14. suggested layout guideline
cs4227 ds281pp2 21 figure 15. 20-bit adc filter response figure 16. 20-bit adc passband ripple figure 17. 20-bit adc transition band figure 18. dac frequency response figure 19. dac passband ripple figure 20. dac transition band
cs4227 22 ds281pp2 2.13 memory address pointer (map) map4-map0 register pointer incr auto increment control bit 0 - no auto increment 1 - auto increment on this register defaults to 01h. 2.14 reserved byte (0) this byte is reserved for internal use and must be set to 00h for normal operation. this register defaults to 00h. 2.15 clock mode byte (1) ce master clock enable 0 - clock enabled 1 - clock disabled ci1-ci0 determines frequency of xti 0 - 256 fs 1 - 384 fs 2 - 512 fs 3 - not used co1-co0 sets clkout frequency 0 - 256 fs 1 - 384 fs 2 - 512 fs 3 - 1 fs this register defaults to 01h. 76543210 incr 0 0 map4 map3 map2 map1 map0 76543210 0co1co0ci1ci0 0 0 ce
cs4227 ds281pp2 23 2.16 converter control byte (2) rs chip reset 0 - no reset 1 - reset cal calibration control bit 0 - normal operation 1 - rising edge initiates calibration the following bits are read only: du shows selected de-emphasis setting used by dac's 0 - normal flat dac frequency response 1 - de-emphasis selected clke clocking system status 0 - no errors 1 - crystal is not oscillating, or requesting clock change in progress calp calibration status 0 - calibration done 1 - calibration in progres this register defaults to 01h. 2.17 dac control byte (3) mut6-mut1 mute control bits 0 - normal output level 1 - selected dac output muted mutc controls mute on consecutive zeros function 0 - 512 consecutive zeros will mute dac 1 - dac output will not mute on zeros zcd zero crossing disable 0 - dac mutes and volume control changes occur on zero-crossings 1 - dac mutes and volume control changes occur immediately. this register defaults to 3fh. 76543210 calp clke du 0 0 0 cal rs 76543210 zcd mutc mut6 mut5 mut4 mut3 mut2 mut1
cs4227 24 ds281pp2 2.18 output attenuator data byte (4, 5, 6, 7, 8, 9) att6-att0 sets attenuator level 0 - no attenuation 127 - 127 db attenuation att0 represents 1.0 db of attenuation this register defaults to 7fh. 2.19 dac status report byte (read only) (10) acc6-acc1 acceptance bit 0 - att6-att0 has been accepted. 1 - new setting is waiting for zero-crossing to be accepted. this register is read-only. 2.20 adc control byte (11) mutl, mutr, mutm - left, right and mono channel mute control 0 - normal output level 1 - selected adc output muted ais1-ais0 adc analog input mux control 0 - selects stereo pair 1 1 - selects stereo pair 2 2 - selects stereo pair 3 3 - differential input is1-is0 input mux selection 0 - stereo adc output to sdout1, mono adc output to sdout2 1 - auxiliary digital input port to sdout1, mono adc output to sdout2 2 - auxiliary digital input port to sdout1, stereo adc output to sdout2 3 - not used. this register defaults to 00h. 76543210 0 att6 att5 att4 att3 att2 att1 att0 76543210 0 - acc6 acc5 acc4 acc3 acc2 acc1 76543210 is1 is0 0 ais1 ais0 mutm mutr mutl
cs4227 ds281pp2 25 2.21 input control byte (12) gnl1-gnl0 sets left input gain 0 - 0 db 1 - 3 db 2 - 6 db 3 - 9 db gnr1-gnr0 sets right input gain 0 - 0 db 1 - 3 db 2 - 6 db 3 - 9 db ovrm adc overflow mask this register defaults to 00h. 2.22 adc status report byte (read only) (13) lvl2-lvl0, lvr2-0 left and right adc output level 0 - normal output levels 1 - -6 db level 2 - -5 db level 3 - -4 db level 4 - -3 db level 5 - -2 db level 6 - -1 db level 7 - clipping lvlm1-lvlm0 mono adc output level 0 - normal output level 1 - -6 db level 2 - -3 db level 3 - clipping these bits are 'sticky'. they constantly monitor the adc output for the peak levels and hold the max- imum output. they are reset to 0 when read. this register is read only. 76543210 ovrm 0 0 0 gnr1 gnr0 gnl1 gnl0 76543210 lvm1 lvm0 lvr2 lvr1 lvr0 lvl2 lvl1 lvl0
cs4227 26 ds281pp2 2.23 dsp port mode byte (14) ddf2-ddf0 data format 0 - right justified, 20-bit 1 - right justified, 18-bit 2 - right justified, 16-bit 3 - left justified, 20-bit in / 24-bit out 4 - i 2 s compatible, 20-bit in / 24-bit out 5 - one data line mode (figure 10) 6 - one data line (master mode only, figure 10) 7 - not used dsck set the polarity of clocking data 0 - data clocked in on rising edge, out on falling edge 1 - data clocked in on falling edge, out on rising edge dms1-dms0 sets the mode of the port 0 - slave 1 - master burst - sclks are gated 128 fs clocks 2 - master non-burst - sclks are evenly distributed (no 48 fs sclk) 3 - not used - default to slave dck1-dck0* set number of bit clocks per fs period 0 - 128 1 - 48 - master burst or slave mode only 2 - 32 - all formats will default to 16 bits 3 - 64 this register defaults to 00h. * ignored in data formats 5 and 6. 76543210 dck1 dck0 dms1 dms0 dsck ddf2 ddf1 ddf0
cs4227 ds281pp2 27 2.24 auxiliary port mode byte (15) adf2-adf0 data format 0 - right justified, 20-bit data 1 - right justified, 18-bit data 2 - right justified, 16-bit data 3 - left justified, 20-bit 4 - i 2 s compatible, 20-bit 5 - not used 6 - not used 7 - not used asck sets the polarity of clocking data 0 - data clocked in on rising edge 1 - data clocked in on falling edge ams1-ams0 sets the mode of the port. 0 - slave 1 - master burst - sclkauxs are gated 128 fs clocks 2 - master non-burst - sclkauxs are evenly distributed in lrckaux frame 3 - not used - default to slave ack1-ack0 set number of bit clocks per fs period. 0 - 128 1 - 48 - master burst or slave mode only 2 - 32 - all input formats will default to 16 bits. 3 - 64 this register defaults to 00h. 76543210 ack1 ack0 ams1 ams0 asck adf2 adf1 adf0
cs4227 28 ds281pp2 2.25 auxilliary port control byte (16) dem 2-0 selects de-emphasis response/source 0 - de-emphasis off 1 - de-emphasis on 32 khz 2 - de-emphasis on 44.1 khz 3 - de-emphasis on 48 khz 4 - de-emphasis pin 32 khz 5 - de-emphasis pin 44.1 khz 6 - de-emphasis pin 48 khz 7 - reserved moh mute on hold 0 - extended hold (16 frames) mutes dac outputs 1 - dacs not muted umv unmute on valid data 0 - dacs unmute when hold is removed 1 - dacs must be unmuted in dac control byte after hold is removed. this register defaults to 00h. 76543210 0 0 umv moh 0 dem2 dem1 dem0
cs4227 ds281pp2 29 3. pin descriptions power supply va+ - analog power input +5 v analog supply. agnd1, agnd2 - analog ground analog grounds. vd+ - digital power input + 5 v digital supply. dgnd1, dgnd2 - digital ground digital grounds. 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 cs4227-kq 44-pin tqfp top view ad0/cs ad1/cdin xti sda/cdout scl/cclk hold dataux lrckaux sclkaux nc dgnd1 vd+ dgnd2 cmout ainaux ain1l ain1r ain2r ain2l ain3l ain3r pdn spi/i2c xto ovl clkout sdin3 sdin2 sdin1 sdout2 sdout1 lrck sclk nc agnd1 va+ agnd2 aout1 aout2 aout3 aout4 aout5 aout6 dem
cs4227 30 ds281pp2 analog inputs ain1l, ain1r - left and right channel mux input 1 analog signal input connections for the right and left channels for multiplexer input 1. ain2l, ain2r - left & right channel mux input 2 analog signal input connections for the right and left channels for multiplexer input 2. ain3l, ain3r - left & right channel mux input 3 analog signal input connections for the right and left channels for multiplexer input 3. ainaux - auxiliary line level input analog signal input for the mono a/d converter. analog outputs aout1, aout2, aout3, aout4, aout5, aout6 - audio outputs the analog outputs from the 6 d/a converters. each output can be independently controlled for output amplitude. cmout - common mode output this common mode voltage output may be used for level shifting when dc coupling is desired. the load on cmout must be dc only, with an impedance of not less than 50 k w . cmout should be bypassed with a 1.0 f to agnd. digital audio interface signals sdin1 - serial data input 1 digital audio data for the dacs 1 and 2 is presented to the cs4227 on this pin. this pin is also used for one-line data input modes. sdin2 - serial data input 2 digital audio data for the dacs 3 and 4 is presented to the cs4227 on this pin. sdin3 - serial data input 3 digital audio data for the dacs 5 and 6 is presented to the cs4227 on this pin. sdout1- serial data output 1 digital audio data from the 20-bit stereo audio adcs is output from this pin. when is = 1 or 2, dataaux is output on sdout1. this pin is also used for one line data output modes. sdout2 - serial data output 2 digital audio data from the mono audio adc is output from this pin. when is = 2, the stereo audio adc's are output from this pin sclk - dsp serial port clock i/o sclk clocks digital audio data into the dacs via sdin1/2/3, and clocks data out of the adcs on sdout1/2. active clock edge depends on the dsck bit.
cs4227 ds281pp2 31 lrck - left/right select signal i/o the left/right select signal. this signal has a frequency equal to the sample rate. the relationship of lrck to the left and right channel data depends on the selected format. dem - de-emphasis control when low, dem controls the activation of the standard 50/15 us de-emphasis filter for either 32, 44.1 or 48 khz sample rates. this pin is enabled by the dem2-0 bits in the auxiliary port control byte. ovl - overload indicator this pin goes high if either of the stereo audio adcs or the mono adc is clipping. auxillary digital audio signals dataux - auxiliary data input dataux is the auxiliary audio data input line, usually connected to an external digital audio source. lrckaux - auxiliary word clock input or output in auxiliary slave mode, lrckaux is a word clock (at fs) from an external digital audio source. in auxiliary master mode, lrckaux is a word clock output (at fs) to clock an external digital audio source. sclkaux - auxiliary bit clock input or output in auxiliary slave mode, sclkaux is the serial data bit clock from an external digital audio source, used to clock in data on dataaux. in auxiliary master mode, sclkaux is a serial data bit clock output. hold - hold control this pin is sampled on the active edge of sclkaux. if it is high any time during the frame, dataux data is ignored and the previous "good" sample is output to the serial output port. control port signals spi /i2c - control port format setting this pin low configures the control port for the spi interface; a high state configures the control port for the i 2 c interface. the state of this pin sets the function of the control port input/output pins . scl/cclk - serial control interface clock scl/cclk is the serial control interface clock, and is used to clock control bits into and out of the cs4227. ad0/cs - address bit / control port chip select in i 2 c ? mode, ad0 is a chip address bit. in spi software control mode, cs is used to enable the control port interface on the cs4227. ad1/cdin - address bit / serial control data in in i 2 c ? mode, ad1 is a chip address bit. in spi software control mode, cdin is the input data line for the control port interface. sda/cdout - serial control data out in i 2 c ? mode, sda is the control data i/o line. in spi software control mode, cdout is the output data from the control port interface on the cs4227.
cs4227 32 ds281pp2 clock and crystal pins xti, xto - crystal connections input and output connections for the crystal which may be used to operate the cs4227. alternatively, a clock may be input into xti. clkout - master clock output clkout allows external circuits to be synchronized to the cs4227. alternate output frequencies are selectable by the control port. miscellaneous pins pdn - powerdown pin when low, the cs4227 enters a low power mode and all internal states are reset, including the control port. when high, the control port becomes operational and the rs bit must be cleared before normal operation will occur. nc - no connect
cs4227 ds281pp2 33 4. parameter definitions dynamic range the ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dbfs signal. 60 db is then added to the resulting measurement to refer the measurement to full scale. this technique ensures that the distortion components are below the noise level and do not effect the measurement. this measurement technique has been accepted by the audio engineering society, aes17-1991, and the electronic industries association of japan, eiaj cp-307. total harmonic distortion + noise the ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 20 hz to 20 khz), including distortion components. expressed in decibels. adcs are measured at -1 dbfs as suggested in aes 17-1991 annex a. idle channel noise / signal-to-noise-ratio the ratio of the rms analog output level with 1khz full scale digital input to the rms analog output level with all zeros into the digital input. measured a-weighted over a 10 hz to 20 khz bandwidth. units in decibels. this specification has been standardized by the audio engineering society, aes17-1991, and referred to as idle channel noise. this specification has also been standardized by the electronic industries association of japan, eiaj cp-307, and referred to as signal-to-noise-ratio. total harmonic distortion (thd) thd is the ratio of the test signal amplitude to the rms sum of all the in-band harmonics of the test signal. units in decibels. interchannel isolation a measure of crosstalk between channels. measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. units in decibels. frequency response a measure of the amplitude response variation from 20 hz to 20 khz relative to the amplitude response at 1 khz. units in decibels. interchannel gain mismatch for the adcs, the difference in input voltage that generates the full scale code for each channel. for the dacs, the difference in output voltages for each channel with a full scale digital input. units are in decibels. gain error the deviation from the nominal full scale output for a full scale input. gain drift the change in gain value with temperature. units in ppm/c. offset error for the adcs, the deviation in lsb's of the output from mid-scale with the selected input grounded. for the dac's, the deviation of the output from zero (relative to cmout) with mid-scale input code. units are in volts.
cs4227 34 ds281pp2 5. package dimensions inches millimeters dim min max min max a 0.000 0.065 0.00 1.60 a1 0.002 0.006 0.05 0.15 b 0.012 0.018 0.30 0.45 d 0.478 0.502 11.70 12.30 d1 0.404 0.412 9.90 10.10 e 0.478 0.502 11.70 12.30 e1 0.404 0.412 9.90 10.10 e 0.029 0.037 0.70 0.90 l 0.018 0.030 0.45 0.75 0.000 7.000 0.00 7.00 typ max typ max coplanarity .001 .004 .025 .10 jedec # : ms-026 44l tqfp package drawing e1 e d1 d 1 e l b a1 a
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